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Inapac's patented Voltage Induced Burn-in
Emulation (VIBE™) is a breakthrough technology that uniquely
enables the integration of DRAM into system-in-package (SiP) by
ensuring high quality and reliability at the die level, without
requiring the traditional oven-based burn-in.
At the core of VIBE is the assertion that electrical stress is
a much more efficient physical phenomena acceleration mechanism
than temperature, and that in fact both stress methods can be used
in concert to obtain optimum results.
Inapac's technologists have devised a special, proprietary, patented
test and stress circuitry which, overlaid with the standard DRAM
logic, can be used to apply appropriate electrical stimuli to each
potential failure point inside the device.
The VIBE circuitry is accessible via a very narrow, high-speed
test path, allowing full test and stress of the Inapac memory device
through a very small number of pins. This way, wafer level test
can be done economically with a high degree of parallelism, and
SiP final test can be done easily even though only a very small
number of pins connect the DRAM directly to the package.
VIBE technology is also embedded in the proprietary test deliverables
engineered by Inapac for each of its memory devices.
For all its novelty, VIBE does not require any change to standard
DRAM processes available at most leading foundries and takes full
advantage of standard test equipment readily available throughout
the industry.
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