Intellectual Property & Services For Reliable SiPs

256Mb LPDDR SDRAM, 32-bit wide, JEDEC JC63 compatible pads

FEATURES

• Doube data rate quad-bank DDR synchronous DRAM
• Commands and Address registered on positive edge of system clock
• Standard LPDDR SDRAM interface using CS/, RAS/, CAS/, and WE/
• Burst length: 2, 4, or 8 
• Sequential burst only
• CAS latency: 2 or 3
• DQS Data Strobes to synchronize data timing
• DMs for WRITE mask
• 8192-cycle refresh, 64ms auto refresh period
• Partial array self-refresh
• Temperature compensated self-refresh
• Deep Power Down
• Programmable Drive Strength
• 1.8V DRAM core voltage
• 1.8, 2.5, or 3.3V I/O voltage

KEY TIMING PARAMETERS

CONFIGURATION