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IT16M32SDL

16Mb SDRAM, 1.8V, 32-bit wide

FEATURES

Single data rate dual-bank synchronous DRAM
All signals registered on positive edge of system clock
Standard SDRAM interface using CS/, RAS/, CAS/, and WE/
Burst length: 2, 4, 8 and full page
Sequential burst only
CAS latency: 2, 3
DQMs for READ/WRITE mask
2048-cycle refresh, 32ms refresh period
1.8V DRAM voltage
1.8V, 2.5V, 3.3V I/O voltage

KEY TIMING PARAMETERS

Clock Speed	Access Time	tRCD	tRP
133 Mhz	6.5 ns	22.5 ns	22.5 ns

CONFIGURATION

Description	16Mb (x32)	16Mb (x16)
Configuration	2048-R x 128-C x 32-bit x 2-banks	2048-R x 256-C x 16-bit x 2-banks
Refresh Count	2048	2048
Row Address	A[0:10]	A[0:10]
Bank Address	BA	BA
Column Address	A[0:6]	A[0:7]

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