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128Mb SDRAM, x16/x32 I/O, 1.8V
FEATURES
- Single data rate quad-bank synchronous DRAM
- All signals registered on positive edge of
system clock
- Standard LPDDR SDRAM interface using CS/,
RAS/, CAS/, and
WE/
- Burst Length: 2, 4, 8 and full page
- Sequential burst only
- CAS latency: 2 or 3
- DQM for READ/WRITE mask
- Partial array self-refresh
- Temperature compensated self-refresh
- Deep Power Down
- Programmable Drive Strength
- 64ms auto-refresh period
- 1.8V DRAM voltage
- 1.8V and 2.5V I/O voltage
- 166MHz Clock
CONFIGURATION
| Description
|
128Mb
(x16) |
128Mb
(x32) |
| Configuration |
2M
x 16-bit x 4-banks |
1M
x 32-bit x 4-banks |
| Refresh Count |
4096 |
4096 |
| Row Address |
A[0:11] |
A[0:11] |
| Bank Address |
BA[0:1] |
BA[0:1] |
| Column Address |
A[0:8] |
A[0:7] |
FUNCTIONAL DESCRIPTION
The Inapac IT128M32SD is a high-speed CMOS
SDRAM containing
134,217,728 bits. It is configured with four banks.
Each bank is organized as 4096 rows. There are 512 columns
on the x16 configuration, and 256 columns on the x32 option. Each
row is selected using A0 to A11,
while a column is selected using A0 to A7 (x32 option) or A0 to A8
(x16 option). Each bank is selected
using BA0 and BA1.
This product is currently under
development.
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