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Inapac’s solution
serves a market opportunity of over a billion units, where
applications such as cell phones and portable consumer devices (MP3
players, Digital Cameras, Handheld games, etc) are forced to
integrate ever-higher memory capacities to maintain a competitive
feature set. Tight system-level constraints over power, space and
performance are forcing silicon vendors to consider SiP
implementations, whereby the application processor (logic device) and
memory (DRAM) are packaged in the same device.
Inapac Technology
has developed a family of System in Package (SiP) optimized
memory I.P. and a proprietary testing platform (SiPFLOW™
) that enables
reliable multimedia capabilities in small form factor devices.
Inapac’s product offerings and business model are specifically
tailored to deliver high volume, reliable SiP devices. The company’s
proprietary
SiPFLOW™
platform
enables cost effective production of SiPs with:
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SiP-optimized memory designs
squarely addressing the needs of the target application
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A comprehensive testing methodology
at the wafer and SiP device level
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A cost effective supply chain
(including memory foundries, assembly and test facilities and
ongoing yield and quality management services over the SiP product
lifecycle)
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Technology and know-how for SiP
package assembly and testing
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A high volume production methodology
ensuring full control over quality and reliability
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Custom test services to lower costs
over the lifecycle of the SiP product
Inapac product
family includes several SiP-optimized memory I.P. offerings. Inapac's
proprietary
SiPFLOW™
platform
offers cost effective memory solutions featuring:
-
Sizes ranging from 16Mb to 256Mb
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Bus widths of 16 bits or 32 bits
- JC63 compliant pads for SiP or
POP/MCP
- Small size packaging
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High-speed versions
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Ultra-low power versions
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Industry leading reliability
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