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availability of fully tested high quality memory in die form is a
critical consideration when developing a system-in-package (SiP)
design. Since the final product yield is a function of the yields of
all of the components together, a single bad die can have a
significant impact on overall cost. Conventional commodity DRAM
cannot be used for SiP integration because of design which relies on
manufacturing methods that minimize testing at the wafer level, and
rely on post-assembly burn-in to reach a suitable quality level.
A typical DRAM burn-in process may require from 16 to
24 hours during mass production. Traditional DRAM burn-in accelerates
failure occurrences through a sharp and prolonged elevation of
temperature. While burn-in is an attractive solution for commodity
memories, it is not a desirable and effective technique for SiPs.
Approaches based on wafer-level burn-in have not so far proven
economical or production worthy for high volume applications.
By contrast, Inapac is delivering the
SiPFLOW™
platform -- consisting of memory IP, testing
infrastructure, and specialized SiP testing services and support --
that addresses the needs of high volume SiP production in a cost
effective manner. Inapac's memory designs are based on proven
manufacturing processes to ensure optimal yield, reliability, power
dissipation and performance. The designs are specifically optimized
for SiP and utilize embedded logic circuitry and comprehensive test
coverage to ensure quality and reliability at both the die and SiP
device level.
With a patented technology called Voltage Induced
Burn-in Emulation (VIBE™),
special circuitry is used to control signals and power supplies inside
the DRAM – in combination with other stress mechanisms – to emulate
the effect of industry standard oven-based burn-in. This can be done
at the wafer level to obtain dies that have the same, or better,
quality and reliability characteristics as packaged commodity
products.
Inapac has also incorporated
SiPLINK™
technology, an innovative architecture and test logic to
enable final tests on the memory die after it has been assembled in
the SiP. This allows for screening out reliability issues that have
been introduced as a result of the SiP assembly steps (wafer thinning,
die bonding, assembly, etc.). A unique benefit of the
SiPLINK™
test is that it does not require any additional pins on the SiP device
to perform extensive memory tests, enabling a smaller footprint of the
SiP. With
SiPLINK™,
Inapac delivers a cost effective, proven testing methodology to
achieve high volume production with industry leading reliability
targets (200 dppm or less).
For all its unique advantages, the integration of
Inapac's proprietary on-chip test circuitry causes a very small die
size increase compared to a traditional commodity device. Overall test
cost is competitive, and the end-quality result is as good as, or
better than, traditional burn-in.
Inapac's
SiPFLOW™
platform has been proven through extensive correlation
studies across a number of products using three manufacturing process
generations based on both stack and trench technologies. The
advantages of Inapac's approach when applied to SiPs are:
-
SiP optimized
memory design (smallest size, low voltage, cost-effective packaging)
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High quality die
with post-assembly test ensuring highest reliability
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Cost effective,
high volume production methodology
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No burn-in
required
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No dedicated pins
required to fully test the memory array
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Only one
high-speed clock pin required for complete performance testing
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Better manufacturing control
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