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Currently,
ASIC vendors are seeking memory die products using Known Good Die (KGD)
methodologies for addressing SiP application needs. What makes the
KGD model complicated is that it is based on non-standard test plans
of various levels of quality and reliability; different vendors
specify different reliability levels. Today, using customized wafer
level burn-in and testing approaches, it may be possible to achieve
KGD reliability levels in the 1000 dppm (defective parts per
million) range. These approaches, in addition to being less cost
effective, lack the capability for thorough testing and screening of
problems within the SiP, i.e. post assembly.
The onus and risk of ensuring
KGD reliability falls on the ASIC vendor. Without a good
methodology, these vendors may find themselves scrapping defective
SiPs at the final manufacturing stages – where the expenditure in
time and raw materials is high and the economic penalty due to
reliability defects can become prohibitive. Inapac’s
SiPLINK™
architecture enables final tests on the memory die after it has been
assembled in the SiP. This allows for screening out reliability
issues that have been introduced as a result of the packaging steps
(wafer thinning, die bonding, assembly, etc.). A number of these
issues are problems that arise because DRAM is essentially an analog
device (capacitor) and is susceptible to parametric failures in the
post-assembly stage. A unique benefit of the
SiPLINK™
test is that it does not require any additional pins on the SiP to
access the DRAM die for these memory tests, enabling a smaller
footprint of the SiP. With
SiPLINK™,
Inapac delivers a cost effective, proven testing methodology to
achieve high volume production with industry leading reliability
targets (200 dppm or less)
HAS YOUR KNOWN GOOD DIE
DIED?
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