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Inapac’s
SiPFLOW™
platform advantage begins with design of a memory product family
with features specifically optimized for SiP integration – small
footprint, low power consumption, high bandwidth operation via a
wide bus interface. Most notably, the platform provides the ability
(called
SiPLINK™)
for testing the memory not only in die form, but also within the
assembled SiP device, enabling customers to achieve high targets for
reliability of the final product.
At the silicon
level, Inapac’s
VIBE™
technology eliminates cumbersome wafer level burn-in testing by
using an optimal combination of voltage and temperature level
stressing. With VIBE™, Inapac delivers an equivalent level of
quality and reliability to temperature level burn-in testing,
without requiring the capital-intensive operational infrastructure.
At the package level, Inapac’s
SiPLINK™
architecture enables final tests on the memory die after it has been
assembled in the SiP. This allows for screening out reliability
issues that have been introduced as a result of the packaging steps
(wafer thinning, die bonding, assembly, etc.). A number of these
issues are problems that arise because DRAM is essentially an analog
device (capacitor) and is susceptible to parametric failures in the
post-assembly stage. A unique benefit of the
SiPLINK™
test is that it does not require any additional pins on the SiP to
access the DRAM die for these memory tests, enabling a smaller
footprint of the SiP. With
SiPLINK™,
Inapac delivers a cost effective, proven testing methodology to
achieve high volume production with industry leading reliability
targets (200 dppm or less).
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