Intellectual Property & Services For Reliable SiPs

Q:  Why do we want to put a DRAM in a SiP over other types of memory?

A:  While other types of memory can and have been used in SiP, DRAM has  the unique advantage of having the highest bit density as well as lowest cost per bit. For the application that does not require non-volatile memory, DRAM is the most commonly used memory type due to its over all cost advantage.

Q:   What factors have impeded the use of DRAM in SiP?

A:  One critical factor with DRAM is that burn-in is required in order to bring DRAM’s reliability – measured in defects per million (dpm) -- down to an acceptable level (typically <500 dpm for most applications). Burn-in is a standard industry practice in a commodity DRAM production flow.  In a SiP, doing a standard package level burn-in is not practical as it can have undesirable secondary effects on the other silicon components within the same SiP. Another key challenge is testing of the memory die after it has been packaged in the SiP.  A test methodology that adequately comprehends testing in the post assembly production process of the SiP is vital in assuring quality and reliability of the SiP device.

Q:  What is burn-in?

A:  Burn-in is a process where you intentionally stress a device by operating it at an elevated temperature (typically 125^oC ambient) and beyond the standard voltage level (typically +10% to +20% depending on the process). The rationale behind burn-in is that since wear out mechanisms have a much higher activation energy than intrinsic and extrinsic defects, elevated voltage and temperature levels will force devices with certain types of defects to break down earlier; i.e. before wearing out the devices during useful life.  For commodity DRAM, burn-in is typically done at the package level by reusing the existing test and burn-in hardware. Depending on the process maturity, level/type of stress and desired quality level, typical burn- in can range from 4 hours up to 20+ hours.

Q:  Why can’t I simply use Known Good Die (KGD) in my SiP, without having to burn-in my SiP?

A: By definition KGD DRAM must have the same level of quality and reliability as a DRAM that has completed a package level burn-in.  However, even though you no longer have to burn-in a KGD, you still want the capability to test it in the SiP production flow to ensure full visibility and control over product quality and reliability levels.

Q:  I thought KGDs do not require final test once they are in SiPs. Why do we want to test DRAM once they are in a SiP?

A: First of all, not all KGDs are created equal. The only way to know how well or poorly a KGD performs in your SiP is to perform the test and/or qualification when it is in your SiP.  Second, DRAMs are fundamentally different in nature than logic devices and exhibit very different failure patterns. Even though DRAMs are used almost exclusively in digital systems, such as PC and servers, the DRAM core is analog at heart (capacitor).  Assembly processes such a backside grind (BSG) or wafer thinning as well as the type of molding compound/die attach can have significant impacts on a DRAM’s parametric performance.  This cannot be determined or predicted until after the completion of the SiP assembly process.

Q:   Why not just test for those parameters during wafer probe?

A:  Basically wafer probe tests are designed to rule out gross functional failures (such as open, short, bank fails, etc.) to avoid incurring assembly costs on the obviously bad dice. The wafer probe tests typically do not cover speed and parametric tests due to the limited capability of the low cost memory tester used for probe.  In addition, the high parasitic of the probe card used limit the amount of parametric test coverage during wafer probe.  Furthermore, since the parametric shifts occur after BSG and package assembly process, the specifications are somewhat unpredictable in parameter as well as in severity.  The strategy of guard banding against all possible shifts for worst-case scenarios runs a very high risk of rejecting dice (over kill) that would have been good once they have been assembled. Finally, while it is not impossible, it is not practical to thin a wafer before wafer probe. The risks of damaging/breaking a thinned wafer during handling and probing are very real and significant.Basically, it is cheaper, easier and more accurate to test for the packaging induced parametric shifts AFTER the SiP assembly process has been completed.

Q:  Why can’t I test the DRAM in the SiP while I am testing my ASIC in the SiP?

A:  The test strategy of DRAM is very different from that of a typical ASIC. An ASIC typically requires a high pin count Automatic Test Equipment (ATE) that can “push” as many test vectors simultaneously as fast as possible. Even though the ASIC test time may be relatively short, depending on the ASIC type and ATE used, often only 1, 2 or 4 devices can be tested at one time. The DRAM, on the other hand, requires a longer test time, but one can test up to 128 devices in parallel, depending on ATE used. In theory, a System on Chip (SOC) ATE can be used to test the DRAM in a SiP. However, since it can only test as many DRAMs as the ATE is set up to test ASICs, it is an extremely inefficient and expensive way to test DRAM.  Testing DRAM within a SiP with specialized memory ATE is the most cost effective method available.

      Q:  Can I use my ASIC to test the DRAM?

A:  While you can use the ASIC to test DRAM in a SiP, it is an extremely inefficient and expensive way to go about it. First, you have to make sure your ASIC is good. Then you can only do basic handshake protocols to detect gross functional failures. Anything beyond that would require a fairly significant effort to program the ATE to use the ASIC to add additional test coverage. This type approach has very limited test coverage and will not cover parametric specifications. In addition, while using the ASIC to test DRAM, the full cost of ASIC ATE test time is being incurred.

Q:  Why do I need to test every SiP?  Why not sample a population and do the tests?

A:  You don’t need to test every SiP all the time. The important part is to have the capability to test every SiP if you need to do so. If sampling can meet your quality objective, it is what you should do as it saves money and reduces your cycle time. The issue arises if you failed sampling. Then you have to change from sampling mode to 100% testing of the production lot from which the sample originated. Again, it is better to have the ability to do 100% testing and not need it than to have the need to do 100% testing and NOT have the capability to do so. So, even you are only doing sampling, you still need to have the 100% testing capability. As a result, it is prudent to perform 100% final testing on all SiPs initially to collect data in order to determine if sampling alone is adequate to meet the target quality level.

Q:  How long do I have to keep the final test on the SiP?

A:  As long as you need to and not a second longer. Final tests can be eliminated once sufficient data has been collected to support the required outgoing quality target. Final tests are designed to provide a means of evaluating the out going quality of products before release in the field. The only other meaningful feedback is through customer returns, which can be significantly more costly than performing final tests.