Intellectual Property & Services For Reliable SiPs

Inapac Technology and ProMOS to Collaborate On 256Mb Mobile DDR DRAM for System-in-Package/Multi-Chip Package Applications

ProMOS to deliver bare die solutions based on Inapac SiPFLOW^TM  methodology

San Jose, CA -- May 30, 2007 – Inapac Technology, Inc. today announced that it has entered into a development agreement with ProMOS Technologies, a leading manufacturer of DRAM products, to develop a low-power 256Mb (megabit) DDR (dual-data-rate) SDRAM based on Inapac’s proven SiPFLOW^TM platform. The product will be manufactured by ProMOS and supplied in KGD (known-good die) form for system-in-package (SiP) and multi-chip package (MCP) devices.

Under the terms of the non-exclusive agreement, the companies are collaborating on a design that uses Inapac’s proven DFT (design-for-test) IP (intellectual property) and testing methodology to optimize the memory for stacked-die applications. ProMOS plans to sample the device in the fourth quarter of 2007 to SiP/MCP manufacturers addressing media-rich mobile products (multimedia cellular handsets, personal media players, etc.).

The Inapac SiPFLOW platform achieves the optimal balance of low-cost production and high reliability for DRAM die. With the DFT approach, Inapac’s proprietary wafer stress and sort procedures streamline production of KGD, and deliver industry-leading final-product reliability levels.

“We are extremely pleased to build on our successful foundry relationship with Inapac that has validated the SiPFLOW methodology across multiple, high-volume products,” said Dr. Ben Tseng , vice president of the sales and marketing group at ProMOS Technologies. “This agreement enables ProMOS to address the needs of the rapidly growing KGD market with significant cost and reliability advantages over traditional KGD approaches.” 

Development Plan

 The 256Mb DDR SDRAM will be optimized for low-power operation in multimedia applications, with 1.8V operation and a wide (x32) data path for high bandwidth. The edge bond pad connections facilitate both SiP and MCP (JEDEC JC-63 PoP) packaging specifications. The device will be manufactured on the ProMOS 0.11-micron, 12-inch process, which is currently in high-volume production.

 The SiPFLOW Platform

 The Inapac SiPFLOW platform addresses the challenges of achieving low-cost production of KGD while ensuring high quality and reliability in the target (packaged) environment. To support these goals, it uses a DFT-based methodology that provides significant cost efficiencies both at the wafer sort and final test steps.

Wafer-level test uses Inapac’s VIBE™ (Voltage-Induced Burn-in Emulation) voltage-based methodology, which is equivalent to traditional oven-based stress testing but eliminates the specialized capital and test cost burden of using elevated-temperature dynamic burn-in approaches.

After assembly, the memory portion of the SiP/MCP can be fully exercised and tested using the Inapac SiPLINK™ test connections. All testing is performed with conventional, high-volume memory test equipment. In addition, the SiPFLOW methodology allows for continuous improvement over the SiP/MCP product lifecycle. With it, test results can be accumulated and analyzed to fine-tune the manufacturing process and to further correlate wafer sort and final test results to achieve increased yield and reliability.

About ProMOS

ProMOS Technologies, Hsin-chu , Taiwan , is a full-blown memory solution provider, and is renowned in the global DRAM industry for its outstanding performance in manufacturing excellence and technology advancement. The company manufactures 

ProMOS and Inapac collaborate on low-power 256Mbit DDR SiP/MCP product high-performance and high-density commodity DRAM memory chips, as well as pseudo- SRAM , lower power SDRAM, and earlier generation memory designed by Inapac. ProMOS is listed on the Taiwan GreTai Securities Market. For more info rmation, please visit www.promos.com.tw.

About Inapac

Inapac Technology, Inc. is a leading provider of memory technology and services for system-in-package (SiP) and Multi-Chip-Package (MCP) solutions. Inapac provides IP and services based on a Design-for-Test (DFT) production methodology to deliver reliable, cost-effective memories. Products based on the company’s proven SiPFLOW™ platform are licensed to semiconductor companies to enhance the performance, quality and reliability of products in the cell phone, consumer audio/video, digital imaging, and storage markets. Inapac is headquartered in San Jose , California with additional offices in Boise , Idaho and Hsin-chu , Taiwan . For more info rmation, visit the company’s website at www.inapac.com.

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