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Inapac
Technology Releases New 16Mb
DRAM
Design for
Mobile
Applications that Reduces SiP/MCP Cost
Design
Optimized to Reduce Stacked Die Memory Integration Cost to Less Than
$0.50
San
Jose, CA, -- April 25, 2007 – Inapac
Technology, Inc., the leading provider of
DRAM
solutions for system-in-package (SiP) and
multi-chip-package (MCP) devices, today announced the release of a
16Mb (megabit) SDRAM design optimized for the mobile handset market.
Based on Inapac’s proven, high-volume SiPFLOW™ platform, the
design incorporates a unique design-for-test (DFT) architecture and
production methodology that enable SiP and MCP producers to minimize
cost of ownership while achieving exceptional levels of production
quality and reliability. Inapac estimates that the total cost of
incorporating the new 16Mb memory die would be less than $0.50 per
SiP/MCP in volume production. This cost-effective integration of 16Mb
of memory into SiPs/MCPs further extends their reach in high-volume
consumer markets, where their average selling price is $5.00 or less.
Inapac’s SiPFLOW platform is licensed to SiP and MCP suppliers
addressing such applications as feature-rich cellular handsets,
personal media players and LCD-based displays.
“Our existing 16Mb SDRAM has enabled more than 50 million SiP
devices with exceptional quality and reliability. The new design
enables smaller packages, lower power and lower-cost
implementations,” said
Naresh
Baliga
, vice president of marketing for Inapac. “The
new design offers a bond-pad-compatible transition from the existing
design, and is manufactured on the proven, high-volume 0.12-micron
DRAM
wafer foundry from ProMOS Technology.
The
16Mb 0.12-micron design will be available for sampling in Q2 2007,
with volume production planned for Q1 2008.
SiP-Optimized Memory Design
The
Inapac
SiPFLOW
platform delivers the
lowest cost of ownership for stacked memory integration. It includes a
family of memory designs, a proven production methodology, and
specialized SiP memory testing services and
support
. The memory designs are
optimized for SiP integration, including small footprint, low power
consumption, and high-bandwidth operation via a wide bus interface.
They feature edge bond pads for flexible stacking options and easier
wire bonding between ASIC and memory dice.
The
memory designs are based on a DFT architecture that includes the
Inapac VIBE™ (Voltage-Induced Burn-in Emulation) technology and
SiPLINK™ test circuits, which
support
economical wafer-level
screening and final testing of memory within the assembled SiP device.
Inapac’s VIBE technology provides considerable cost savings relative
to high-temperature dynamic wafer-level burn-in testing because it
does not require specialized testing equipment. After assembly, the
memory portion of the SiP can be thoroughly tested through the SiPLINK
test gateway to ensure that quality and reliability targets are
maintained.
Inapac’s
unique SiPFLOW methodology, combined with an IP-based business model,
delivers cost efficiencies, quality and reliability beyond traditional
KGD (Known-Good Die) approaches.
About Inapac
Inapac Technology, Inc. is a leading provider of memory
technology and services for SiP (system-in-package) and MCP
(multi-chip-package) solutions. Inapac provides IP and services based
on a DFT (design-for-test) production methodology to deliver reliable,
cost-effective memories. Products based on the company's proven
SiPFLOW™ platform are licensed to semiconductor companies to enhance
the performance, quality and reliability of products in the cell
phone, consumer audio/video, digital imaging, and storage markets.
Inapac
is headquartered in San Jose, California, with additional offices in
Boise, Idaho, and
Hsin-chu
,
Taiwan
.
For more
info
rmation,
visit the company's website at www.inapac.com.
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