Intellectual Property & Services For Reliable SiPs

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Inapac Technology Inc

Inapac's IP and service offerings are used by leading semiconductor companies for SiP solutions in media rich consumer applications such as, multimedia cell phones, consumer audio/video portables, handheld games, LCD displays and flat panel TVs. Inapac is headquartered in San Jose , California with additional offices in Boise , Idaho and Hsinchu, Taiwan.(www.inapac.com)

Employment – Research and Development

 

Senior DRAM Design Engineer

Requirements:

  • At least 7 years circuit/memory design experience.

  • Must have excellent knowledge of transistor level circuit design

  • Experience in high density synchronous DRAM design is desired

  • Knowledge of DRAM Process technology a plus.

  • Must be able to lead a project from Specification to Tape out

  • BSEE or higher

 Please email your resume to  careers@inapac.com

DRAM Design Engineer

Requirements:

  • At least 3 years circuit/memory design experience.

  • Must have sound knowledge of transistor level circuit design

  • Experience in high density synchronous DRAM design is desired

  • Knowledge of DRAM Process technology a plus.

  • BSEE or higher.

 Please email your resume to  careers@inapac.com

Senior Design Verification Engineer

Requirements:

  • At least 7 years IC design and verification experience

  • Must have good understanding of gate/transistor level circuit

  • Experience in writing DRAM memory models desired

  • Experience in nc-verilog, modelsim, unix, script writing

  • BSEE or higher.

 Please email your resume to  careers@inapac.com

Senior Mask Design Engineer

Requirements:

  • At least 7 years layout experience in high-density memory.

  • Experience in hierarchical memory array construction.

  • Experience in sub-micron design layout.

  • Experience in LVS and DRC

  • Experience in writing LVS/DRC rules a plus

  • BSEE or equivalent

Please email your resume to  careers@inapac.com 

CAD/Design Support Engineer

Requirements:

  • At least 5 years practical CAD experience

  • Experience with Cadence Design Environment, Mentor Calibre, Hspice, HSIM Tools

  • Strong understanding of IC design flow and Deep Sub-micron issues

  • Experience in writing LVS/DRC rules desired

  • Strong verbal and written communication skill desired

  • BS or higher in EE or CS

 Please email your resume to  careers@inapac.com

 

Employment – Operations

     Semi-conductor Memory Customer Engineers

Seeking self-motivated and responsible Customer Engineer with excellent communication skills--one whom enjoys challenges--to join our Customer Response Team.

   Job Description/Responsibilities:

  • First line technical support for any customer issue

  • Attend regular customer meeting as technical window

  • Publish technical report for customer

  • Coordinate internal engineering resources for speedy customer response

  • Maintain a positive attitude for any customer correspondences

Requirements/Skills:

  • BS EE  and/or 5 years experience in DRAM engineering environment is preferred

  • Comprehensive understanding of semi-conductor manufacturing flow is required

  • Experienced in memory design environment is a plus

  • Experienced in memory tester usage/programming, especially Advantest Memory Testers, is a bonus

  • Excellent technical writing and communication skills are required

  • Proficiency in the use of Microsoft Office Tools (Excel, Word, Power Point, Project) is required

  • Occasional travel to customer site is required

 Please email your resume to  careers@inapac.com 

     Semi-conductor Memory Product Engineers

Seeking self-motivated, responsible, and creative Product Engineers with good communication skills to expand our team in Boise , Idaho .  Number one priority/goal is to help improve product yields while simultaneously lowering production costs without sacrificing the product’s quality and reliability.

   Job Description/Responsibilities:

  • Debug semi-conductor memory designs

  • Prepare designs for qualification and production ramp

  • Solve all sorts of yield/reliability issues from product fabrication (wafer level) to customer returns (Multi-chip level)

    Requirements/Skills:

  • BS EE  and/or 3 years experience as PE in DRAM manufacturing environment is preferred

  • Comprehensive understanding of semi-conductor device physics and circuit design is a must

  • Experienced in memory tester usage/programming especially Advantest Memory Testers is a plus

  • Skilled in Cadence Hspice/Verilog and/or KLA ACE is a bonus

  • Inapac operations are worldwide so the ability to travel on a short notice is required (not frequent)

Please email your resume to  careers@inapac.com 

 

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